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What is the Risc in Computer Architecture?

An essay discussing CISC and RISC computer hardware design philosophies and the relevance of both architectures in today's computer systems. Computer architecture is a way of looking at the fundamental operational structure of the computer. It is the blueprint of the requirements and design implementations for the various parts of a computer ' focusing largely on the way by which the central processing unit of the computer (CPU) performs internally and accesses addresses in computer memory. The key to a successful computer system is to select and interconnect computer hardware components that results in that a functional, cost-effective performance-driven machine.

Computer Hardware Architecture Design Architecture is a way of looking at the fundamental operational structure of the computer. It is the blueprint of the requirements and design implementations for the various parts of a computer - focusing largely on the way by which the central processing unit (CPU) performs internally and accesses addresses in memory. The key to a successful computing system is to select and interconnect hardware components that results in that a functional, cost-effective performance-driven machine. The topic of computer architecture addresses this. Instruction set architecture; Computer organization and System Design are three underlying aspects which need to be addressed [1]. I will now discuss two CPU design philosophies which represent two controversial architectural philosophies [2].

CISC (Complex Instruction Set Computer) Processor Architecture A 1960s architect who took the CISC (Complex Instruction Set Computer) approach was an architect who could build a computing system that would utilize the smallest amount of assembly code possible [3]. Armed with fresh innovation in a world of growing technological advancement at his disposal, and the Modus operandi of reducing the level of code, a CISC architect would strive to build as much of the "coding" as possible into the computers hardware itself. An "Intelligent" and "logical" processor hardware system which could "understand" high-level instructions would have huge cost-cutting implications by enabling the use of minimal lines of code to achieve maximum computer functionality and complete any computing task.

A CISC system would contain a Microprocessor instruction set so that each single instruction can execute several low-level operations such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. For a specific task, a CISC processor would come prepared with a specific instruction, e.g. "ADD".

Take a look at a working example to see how powerful and economical this system was:

ADD 2:3
First of all, two values are loaded into separate register
Then, the operands are added in the exception unit
Finally, the sum is stored in the associated register At the very heart of CISC is a set "complex" instruction like ADD. The computer's memory banks are directly operated on [3], thus making the loading or storing functions redundant. ADD is similar to what a programmer in C++ or any other high-level language would code. Takes control over thousands or millions of transistors, CPU etc. One of the primary advantages of this system is that the compiler has to do very little work to translate a high-level language statement into assembly. Micro program instruction sets can be written to match high-level languages and the compiler does not have to be as complicated. Minimal lines of coding must also have reduced the probability of errors in the code, thus reducing cost and debugging-time. In addition, small code sizes could be stored easily to enable a frugal use of RAM [3].

CISC seemed like such a natural and intuitive system at the time and it didn't even have a name. The term was retroactively coined [4] in contrast to reduced instruction set computer computers of the 1970s (although we also have examples of pre-RISC systems of the 1960s) which eventually brought CISC (Complex Instruction Set Computer) to its knees and forced CISC-philes to defend and debate with their adversaries.
RISC (Reduced Instruction Set Computer) Architecture Design The RISC-brigade strive for an instruction set reduced both in size and complexity of addressing modes which they argue enables easier implementation, greater instruction level parallelism, and more efficient compilers [5]. A RISC architect tries to keep the instruction set as simple as possible [6] so that a job can be executed within one clock cycle. Because all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining is possible [7]. Rather than using an "intelligent" hard-coded CPU hardware system, there is more emphasis on the software. Every slight small hardware job can be managed and customized by the software used. So, to add two integers,
LOAD A, 2:3
LOAD B, 5:2
ADD A, B
STORE 2:3, A "LOAD" moves data from the memory bank to a register; "ADD" finds the sum of two operands located within the registers; and "STORE" moves data from a register to the memory banks. They support only register-to-register operations and a few simple addressing modes. In using three instructions codes to achieve only one task, larger amounts of RAM would be needed to store the assembly code, and the compiler would need to do more work to convert that code to a lower-level form. However, this is balanced by the more economical use of registers by means of a set of "reduced instructions" which incorporate a reduced amount of transistors; and as already mentioned, by maximizing the number of instructions per program, the number of clock cycles per second is reduced. So, by using a number of small instructions rather than one "large" instruction, the amount of actual work done by the machine is reduced.

If there were any advantages in this system, the RISC people certainly had their work cut-out for them at first. RISC chips weren't in wide-circulation until the 1970s. Much of the software available at the time was designed for CISC machines. It would have been a commercial risk to actually start mass-producing this technology. RISC & CISC Architecture in Today's Computer Systems In the early years, there appeared more of a distinction between the two designs than appears today.
Systems designed on the RISC philosophy included IBM's System/360 (1964) which was the first commercially available micro programmed computer architecture latter to become known as CISC architecture. The success of System/360 resulted in CISC architectures dominating computer, and later microprocessor, design for two decades. Other CISC computers included VAX (mid-1970s); PDP-11 (1970s); and the Motorola 68000 series (1970s). CISC was also an influence on the Windows 3.1 (1992) and Windows 95 were designed with CISC processors in mind [3] If pure CISC design is not commonly used in today's computing systems, it may have to do with the following: [8]:
Increasing instruction set & chip hardware complexity leads backward-compatibility issues
Variable length instructions slow down the overall performance of the machine
Many specialized instructions are15 not used frequently
CISC instructions typically also set the condition codes as a side effect Whatever the disadvantages in CISC usage, it took at least 10 years for RISC to take commercial hold [3] as Intel was one roadblock to its widespread implementation as Intel (a CISC user) had vast resources to continue implementing the CISC model.

Although RISC is often thought of as a more recent development, in fact the first system which could now be considered as RISC-based was the CDC 6600 supercomputer, designed in 1964 [9]. But the first major RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s [10]. More modern systems were Apple's Power Macintosh line (1994) Windows NT (1993) was RISC compatible.

Nowadays, CISC and RISC conflict has ended with some factions claiming that RISC has won [2], and have more or less converge. Examples of convergences include [11]:
With an increase in processor speeds, CISC chips are now able to execute more than one instruction within a single clock which enables RISC-like pipelining.
We can fit many more transistors on a single chip thus providing more space to execute CISC-like commands. Although today, it is proposed that Intel x86 is the only chip which retains pure CISC architecture [10] it is however at least as fast the fastest true RISC single-chip solutions available [12]. How the two are compared depends on whether a qualitative comparison or a quantitative comparison is made [13].

This author concludes that nowadayas, both architectural designs having little difference, nor much significance between themselves.

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